1. Field of the Invention
The present invention relates to an exposure technique for exposing a substrate such as a wafer, and a device-producing technique for producing, for example, an electronic device such as a semiconductor device or element and a liquid crystal display device or element by using the exposure technique.
2. Description of the Related Art
An exposure apparatus, which includes, for example, a projection exposure apparatus based on the step-and-repeat system (so-called “stepper”) and a projection exposure apparatus based on the step-and-scan system (so-called “scanning stepper” (referred to as “scanner” as well)), has been hitherto used in the lithography step for producing an electronic device (microdevice) such as a semiconductor device or element (for example, the integrated circuit) and a liquid crystal display device or element.
In the lithography step for producing the semiconductor element or the like, patterns of multilayered circuits or the like are overlaid and formed on a wafer. If the pattern overlay accuracy (hereinafter simply referred to as “overlay accuracy”) is unsatisfactory between the respective layers, then the semiconductor element or the like cannot exhibit a predetermined circuit characteristic, and the yield is lowered. Therefore, in ordinary cases, marks (alignment marks) are previously affixed to a plurality of shot areas on the wafer respectively to detect the positions of the marks (coordinate values) on a stage coordinate system of the exposure apparatus. After that, the wafer alignment is performed, based on mark position information and known position information of a pattern (for example, a reticle pattern) to be newly formed, such that one shot area on the wafer is subjected to the alignment with respect to the pattern.
In consideration of the balance of the throughput, the global alignment has been principally used as the system for the wafer alignment wherein the alignment marks are detected for only some shot areas on the wafer (referred to as “sample shots” or “alignment shots” as well) to determine the regularity of the arrangement of the shot areas, thereby subjecting the respective shot areas to the alignment. In particular, the enhanced global alignment (EGA) is dominantly used among the global alignment, wherein the arrangement of shot areas on the wafer is precisely calculated by means of a statistical technique, as disclosed, for example, in Japanese Patent Application Laid-open No. 61-44429 (U.S. Pat. No. 4,780,617).
In a conventional alignment based on the EGA system, the coordinate values of the marks affixed to a predetermined number of the alignment shots are measured to determine a parameter such as the wafer scaling (linear expansion and contraction) based on the measurement result, and the parameter is used so that the arrangement coordinates of all of the shot areas on the wafer are calculated and the adjustment is made for the projection magnification of the projection optical system, etc.
However, the parameter is gradually changed also during the exposure of the wafer, for example, due to the influence of the thermal energy or the like of an exposure light (exposure light beam) radiated, although the change is slight. Therefore, it is feared that an actual coordinate value of the shot area of the wafer or a size of the circuit pattern in the shot area might be gradually changed with respect to the result of the alignment during the exposure, and thus the overlay accuracy might be lowered or deteriorated. Such change of the parameter during the exposure of the wafer as described above has been hitherto considered to such an extent that the change is negligible. In future, however, a fine and minute structure or arrangement of the integrated circuit will be further advanced. In such a situation, it is necessary to consider the change of the parameter during the exposure of the wafer as well, in order to achieve the required overlay accuracy.